The present invention relates generally to digital data processing systems, and more particularly to a clock generator system that produces a number of clock signals, some of a frequency different from the others.
Data processing systems constructed today often use a number of individual integrated circuit component mounted on printed circuit boards and electrically interconnected to one another. For synchronous operation of data processing systems there is often also provided source of a digital clock signal that is distributed to the integrated circuit devices mounted on that board. For lower frequency clock signals (e.g., clock signals on the order of 1 Mhz and less), clock skew may not be a significant problem. However, as systems are developed to use clock frequencies that are much higher (e.g., greater than 1 Mhz) clock skew (i.e., the difference between the occurrence of a transition of a clock signal as seen at points relative to that occurrence at another point) can become a significant problem.
One solution is to handle information transfers between integrated circuits asynchronously through intermediate registers or the like. Another approach is to use phase locked loops (PLLs), but these devices often require a reference signal in order to maintain a phase relation between the reference and the output clock signals. At times, there is jitter encountered between the clock signals of the comparison that create a jitter in the output signals. In addition, PLLs that are implemented in analog form tend to be susceptible to power supply noise. In addition, analog PLLs require additional components.